A static random-access memory (SRAM), which is one of conventional semiconductor devices, will be described with reference to a circuit diagram in FIG. 6.
As shown in FIG. 6, memory cells 100 are disposed in an array and are each connected to a word line WL and to a pair of bit lines (BIT, NBIT).
As shown in FIG. 7, the memory cell 100 has a total of six transistors, i.e., two PMOS transistors MP1 and MP2 provided as load transistors, two NMOS transistors MN1 and MN2 provided as drive transistors, and two NMOS transistors MN3 and MN4 provided as transfer transistors, whereby a memory cell of an SRAM is formed.
That is, the gates of the two transfer transistors MN3 and MN4 are connected to the word lines WL, and the drains of the transfer transistors MN3 and MN4 are respectively connected to the pair of bit lines BIT and NBIT. The sources of the two load transistors MP1 and MP2 are connected to VDD (power supply potential), while the sources of the two drive transistors MN1 and MN2 are connected to VSS (ground potential). The drain of the load transistor MP1 is connected to the source of the transfer transistor MN3, the drain of the drive transistor MN1, the gate of the load transistor MP2 and the gate of the drive transistor MN2. Also, the drain of the load transistor MP2 is connected to the source of the transfer transistor MN4, the drain of the drive transistor MN2, the gate of the load transistor MP1 and the gate of the drive transistor MN1.
As shown in FIG. 6, a precharge circuit 103, a readout column selector 104 and a write column selector 701 are connected to the pair of bit lines BIT and NBIT, and two PMOS transistors MP5 and MP6 for inverting data DATA and NDATA held by the memory cell 100 are also connected to the pair of bit lines BIT and NBIT. The sources of these transistors MP5 and MP6 are connected to VDD; the gate of the transistor MP5 is connected to the bit line NBIT; the drain of the transistor MP5 is connected to the bit line BIT; the gate of the transistor MP6 is connected to the bit line BIT; the drain of the transistor MP6 is connected to the bit line NBIT.
The precharge circuit 103 is constituted by three PMOS transistors MP7, MP8, and MP9. A precharge signal NPC is input to each of the gates of the PMOS transistors MP7, MP8, and MP9. The transistor MP7 has its source connected to VDD and its drain connected to the bit line BIT. The transistor MP8 has its source connected to VDD and its drain connected to the bit line NBIT. The transistor MP9 has its source and drain connected to the bit lines BIT and NBIT, respectively.
The readout column selector 104 is constituted by two PMOS transistors MP3 and MP4. A readout column selecting signal CR is input to each of the gates of the PMOS transistors MP3 and MP4. The transistor MP3 has its drain connected to the bit line BIT, while the transistor MP4 has its drain connected to the bit line NBIT. The transistors MP3 and MP4 have their sources connected to the readout circuit 105. The readout circuit 105 is connected to the bit lines BIT and NBIT through the readout column selector 104.
The write column selector 701 is constituted by two NMOS transistors MN7 and MN8. A write column selecting signal CW is input to each of the gates of the NMOS transistors MN7 and MN8. The transistor MN7 has its drain connected to the bit line BIT, while the transistor MN8 has its drain connected to the bit line NBIT. The write circuit 702 is constituted by two NMOS transistors MN9 and MN10. The sources of the transistors MN9 and MN10 are connected to VSS. Inverted data of data DI to be written is input to the gate of the transistor MN9, while data DI to be written is input to the gate of the transistor MN10. The source of the transistor MN7 and the drain of the transistor MN9 are connected to each other. The source of the transistor MN8 and the drain of the transistor MN10 are connected to each other.
The operation of the semiconductor memory device having the above-described configuration will be described with reference to FIG. 8 with respect to writing at a voltage lower than a normal voltage.
When writing is started, the precharge signal NPC is made inactive to cancel precharge on the pair of bit lines BIT and NBIT. Simultaneously, the write column selecting signal CW is made active to pull down one of the potentials on the pair of bit lines BIT and NBIT from VDD according to the data signal DI and the inverted data NDI of the data DI.
At this time, since the drive power of the transistors are reduced due to the lower voltage, one of the potentials on the pair of bit lines BIT and NBIT cannot be sufficiently pulled in the period in which the word line WL is active, resulting in failure to invert the data DATA and NDATA held by the memory cell 100, as shown in FIG. 8.
To solve this problem, a method of setting the word line WL activation period (pulse width) longer may be used to sufficiently pull the potentials on the pair of bit lines BIT and NBIT so that the data DATA and NDATA held by the memory cell 100 are inverted.
For example, JP2001-196904A discloses an invention for adjustment of the pulse width in a wide operating voltage range.
However, if the word line WL activation period (pulse width) is increased to correspond to a lower voltage, there is a problem that the word line WL activation period is made to be longer than necessary at the normal voltage, causing reduction in operating frequency. There is also a problem that a need arises for an external command according to the operating voltage.
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of performing a high-speed write operation at a lower voltage, without increasing the word line activation period at the normal voltage.